In the field of semiconductor fabrication, critical dimensions of integrated circuits continuously decrease with development of ultra-large scale integration (VLSI). To better adapt to the decreased critical dimensions, lengths of channels in metal-oxide-semiconductor field-effect transistors (MOSFETs) also continuously decrease. However, a distance between a source and a drain of a device also decreases when the channel length decreases. Correspondingly, the controlling ability of the gate structure over the channel becomes worse, and it also becomes harder for the gate voltage to pinch off the channel. As a result, sub-threshold leakage, also known as a short-channel effect (SCE), may easily occur.
To better adapt to the decreased critical dimensions of the devices, the semiconductor process has been gradually transferred from planar MOSFETs to more efficient non-planar three-dimensional transistors, such as fin field effect transistors (FinFETs). In an FinFET, the gate structure is able to control an ultra-thin part (fin) from two sides of the fin, to provide a much stronger controlling ability on the channel and to effectively suppress the short-channel effect compared to the planar MOSFETs. Moreover, compared with other devices, FinFET is more compatible with the present fabrication processes for integrated circuits.
However, the performance of conventionally fabricated FinFET devices still needs to be improved. The disclosed devices and methods are directed to at least partially alleviate one or more problems set forth above and to solve other problems in the art.